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{'doi': '10.2200/s00070ed1v01y200611cac002', 'member_id': '297', 'member': 'Springer Science and Business Media LLC', 'container-title': 'Synthesis Lectures on Computer Architecture', 'primary-resource': 'http://www.morganclaypool.com/doi/abs/10.2200/S00070ED1V01Y200611CAC002', 'tld': 'morganclaypool.com', 'clearbit-logo': 'https://logo.clearbit.com/morganclaypool.com', 'coaccess': [], 'multiple-resolution': [], 'type': 'JOURNAL ARTICLE', 'published_date': 'January 2006', 'publication': 'Synthesis Lectures on Computer Architecture', 'supplementary_ids': '10.2200/S00070ED1V01Y200611CAC002', 'title': 'Transactional Memory', 'name': None, 'id': None, 'location': None, 'display_doi': 'https://doi.org/10.2200/s00070ed1v01y200611cac002', 'grant_info': None, 'editors': None, 'authors': 'James R. Larus | Ravi Rajwar', 'chairs': None}
https://doi.org/10.2200/s00070ed1v01y200611cac002
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Total 29 GB
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